System-level Design and Chip Architecture for Low-Power ICs
Techtorial & Workshop
Decisions and tradeoffs made during the early, pre-synthesis stages of the design cycle ultimately yield the greatest impact on the size, power consumption, performance, and cost of any SoC. It is during these early stages that design teams realize the greatest benefits by carefully analyzing and characterizing tradeoffs among different system-architecture and micro-architecture options.
As the recognized industry leader in automation of advanced low-power design techniques, Cadence has driven innovation and industry awareness of these techniques through its work in the Power Forward Initiative (www.powerforward.org). Cadence has recently extended its low-power support to Cadence system-level planning/design/analysis tools--InCyte Chip Estimator, C-to-Silicon Compiler, and Palladium Dynamic Power Analysis. These tools working in concert enable designers to plan the area, timing and power of a design. They can then feed optimized RTL and design-constraints into Cadence® Encounter® RTL Compiler, and utilize its design exploration capabilities for micro-architecture optimization.
This techtorial and workshop provides an in-depth survey of the Cadence system-level design solution for low power, and gives designers an opportunity to “test-drive” these tools on actual designs. Catch a glimpse of what you can expect at this event.
Who should attend
The techtorial portion (morning) is intended for system and chip architects, designers and technically oriented managers wanting a technical overview of how Cadence tools work together to enable low power design. The lab/workshop portion (afternoon) is geared toward experienced system and chip architects and hardware designers wanting a "hands-on" opportunity to apply the concepts/tools discussed in the morning on actual designs.
What you will learn
The techtorial/workshop will cover the Cadence System-Level and Chip Architecture Low-Power Design solution and will educate the audience about how to:
•Estimate IC size, power, leakage, performance and cost with InCyte Chip Estimator to rapidly analyze options across design architecture, IP, and manufacturing processes pre-RTL and establish the design specifications for downstream implementation steps
•Transform re-usable C/C++/SystemC models into optimized synthesizable RTL with power, area, and performance micro-architecture tradeoffs, using Cadence C-to-Silicon Compiler
•Analyze dynamic power consumption using real-world stimulus across the different elements of your design using Cadence Palladium DPA
•Explore performance, power, and area of different power architectures using RTL and constraints to refine the chip architecture before synthesis, using RTL Compiler design exploration capabilities
Agenda
8:30-9:00am Registration; Continental Breakfast
9:00-9:30am Cadence System-Level/Chip Architecture Low-Power Solution Overview
9:30-10:20 Chip Planning, Estimation and Analysis, Including Pre-RTL Power Tradeoffs
10:20-10:30 (Break)
10:30-11:20 HLS of C/C++/SystemC Models for Low Power
11:20-11:50 SoC (HW and SW) Dynamic Power Analysis with Real-World Stimulus
11:50-12:40 RTL-Based Design Exploration of Timing, Power, and Area
12:40-1:10 Lunch
1:10-3:10 Labs/Workshops (1st session) –High-Level Synthesis –Chip Planning/Estimation
3:10-3:25 (Break)
3:25-5:25 Labs/Workshops (2nd session) –High-level Synthesis –Chip Planning/Estimation
For the afternoon labs/workshops Cadence will provide laptop computers, allowing students to work through a tutorial-based manual with assistance from our Field Applications Engineering team.
Prerequisite: Assumes working knowledge of IC design flows/methodologies.
