Presenter(s): Howard Martin (Zocalo-Tech)

Overview:  Assertions serve as executable specifications describing the required and forbidden behavior of the design.  The assertions are checked in every simulation run by binding assertion checkers/monitors to the design code.   Assertion Based Verification (ABV) represents a major advance in functional verification methodology in the never ending challenge to keep up with chip complexity.    Surveys indicate that utilizing ABV can significantly reduce the verification cycle by cutting debug time in half.  In spite of positive results, wide scale acceptance has been slower than expected.   Successful ABV is dependent on both designers and verification engineers providing assertion checkers on a cost effective basis.   Although the issues for designers and verification engineers are different, the basic problem is same.  Creating, debugging, using and reusing assertion checkers is difficult and time consuming. This impacts the cost effectiveness of ABV resulting in limited acceptance.

This presentation defines how this problem is being addressed for both designers and verification engineers by Zocalo Tech product set, branded under the name Zazz.   Zazz has been architected and developed from the ground up with one goal in mind increased   productivity for engineers adopting and utilizing Assertion Based Verification (ABV).

Cost: Free!

Presenter(s): James Keithan (Design Flow Consultant)

Overview:  With the convergence of front end design verification towards the class libraries of the OVM, it brings to bear another powerful and at times complex tool. It adds a key piece to the set of tools, processes, and flows available to the engineering manager. But how does it fit? Where and when is it applied in the design, test, produce cycle? What tools complement it and where are they applied? This paper discusses a companies transition from directed to random verification techniques. It highlights OVM by describing the trials and triumphs of adopting a standard flow. It shows what tools, such as formal verification, are appropriate where in the flow. How they compliment each other and how they might provide conflicting results. This paper is targeted at Engineering managers, verification managers, and lead verification engineers. It provides an understanding of how new tool offerings fit together, how they provide a standard flow, and where and how to apply which technology to verify their product.

Cost: Free!

Presenter(s): Matan Vax (Cadence Design Systems)

Cost: Free!

Presenter(s): Paul Carzola (Cadence Design Systems)

Overview:  In this techtorial well begin with understanding the verification challenge and what is achieved with feature planning and peer review sessions.  We'll also cover how to use Enterprise Planner to develop executable verification plans that can be instantly loaded in Enterprise Manager to report real time results reflected back onto the plan.  We will also cover how to develop reusable vPlans that can be used both at a block and system level environments while using automation to easily update the mapping patterns to reflect the different testbench hierarchies.

Cost: Free!