Presenter(s): Thomas Whipple (Cadence Design Systems)

Overview:  This session introduces distributed IC-Package co-design which enables distributed IC and package teams to efficiently minimize IC and package design time and costs. It does this by the sharing of key information and functionality between the IC and package design fabrics without forcing designers to learn the other design environment tools. A key requirement is a compact definition of a die and package abstract. The abstracts contain all the necessary information to optimize the IC/package boundary and maximize routability between the fabrics. The die abstract includes information like die boundary, bumps, bump assignments, I/O drivers, RDL routes, and placement blockages from either a digital or analog chip. The package abstract contains wirebond finger and package ball information. Each tool will display the abstracts of the other dies and package. IC and package tools have been enhanced to allow edits to the abstract information from the dies and package. The package tool optimizes I/O driver placement or net assignment to bumps to enhance package routability. Inside a multi-die SiP design, the digital IC tool optimizes net assignments to the bumps of another chip placed face down on top of the die. Direct collaboration between the analog and digital design tools is also enabled. Thus, digital IC, analog IC, and package teams can make suggested changes to each other.

Cost: Free!

Presenter(s): Suresh Subramanian (Tabula), Bala Vishwanath, Swagato Chakraborty, Dipanjan Gope, & Vikram Jandhyala (Physware)

Overview:  Modern programmable logic chips packages provide multiple hundreds of user I/Os switching at 100s of MHz. More advanced devices include dozens of SerDes channels with switching speeds in the multi-gigabit ranges. The situation is further exacerbated by the presence of multiple I/O power rails and high current density core logic. This creates enormous challenges, in designing robust power delivery networks (PDN), on the package. The common metrics for a robust PDN include low impedance and immunity to simultaneous switching output noise. Managing this design complexity requires access to modeling tools that offer the ability to extract and analyze complex 3D structures and provide accurate answers. This session will demonstrate, through a test package, excellent simulation to measurement correlation of various PDN structures. Full-wave electromagnetic solution has been widely used to characterize the PDN. However, due to the ever-increasing complexity of the PDN, the prior EM techniques are all based on approximation by either assuming TEM wave propagation within power/ground planes or geometrical segmentation. On the other hand, Physware PhysWAVE uses 3D full-wave accelerated boundary element techniques and, as will be shown, provides accurate and scalable solution for PDN characterization from DC to high frequencies in a single efficient and accurate scalable solver. In terms of tool flow, Allegro Package Designer (APD) is employed for package layout generation. The .mcm file is directly imported to PhysWAVE. The desired power net, which can be either core or I/O, can be extracted and simulated. Ports are defined between the bump or BGA ball pin and the ground pin, which matches the measurement setup. PhysWAVE outputs S-parameters covering the desired frequency range. Having achieved satisfactory calibration of the tools, the methodology is established to improve the PDN structures through design optimization and to use the tools to predict performance through simulations. It is expected that such a full-wave 3D tool flow, for the first time based on a rigorous 3d EM full-wave solver, will become necessary across many designs in the space of broadband PDN analysis and design for complex-chip packages.

Cost: Free!