With ASICs and even FPGAs now in the multi-million gate range, verification engineers need to generate and manage thousands of tests, deal with frequent spec changes, review project plans, and coordinate multiple teams/sites. Teams must begin projects “with the end in mind” by implementing verification metrics directly tied to the specification that are closely tracked throughout the project. As metrics are captured in an easy to read, executable form, the verification process (along with all the supporting stimulus generation, simulation, and debug activities) becomes much more automated. This seminar will illustrate "coverage-driven verification" techniques that offer higher levels productivity, predictability, and product.