Low Power Techtorials
Power Reduction Design Techniques
A Practical, Proven, Holistic Methodological Approach
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This unique free techtorial is structured with a seminar in the morning and two hands-on workshops in the afternoon to choose from.

Design with power hands-on workshop features the following technologies: Incisive® Design Team Simulator, Encounter® RTL Compiler global synthesis, Encounter Conformal® Low Power

Low-power implementation hands-on workshop features the following technologies: Encounter RTL Compiler global synthesis, Encounter Conformal Low Power, SoC Encounter™ RTL-to-GDSII system, VoltageStorm® power and power rail verification

System-level Design and Chip Architecture for Low-Power ICs
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This techtorial and workshop provides an in-depth survey of the Cadence system-level design solution for low power, and gives designers an opportunity to “test-drive” these tools on actual designs.