The Cadence Low-Power Solution is production proven and has helped many companies achieve their project goals by helping them incorporate low-power design techniques without sacrificing performance while reducing costs and mitigating both schedule and chip functionality/quality risks. Learn how Cadence and other major companies are taking an innovative approach in successfully solving this rising critical customer challenge. Join us and listen to some of the industry's top experts in the field of low power.

This unique free techtorial is structured with a seminar in the morning and two hands-on workshops in the afternoon to choose from.

Design with power hands-on workshop features the following technologies: Incisive® Design Team Simulator, Encounter® RTL Compiler global synthesis, Encounter Conformal® Low Power

Low-power implementation hands-on workshop features the following technologies: Encounter RTL Compiler global synthesis, Encounter Conformal Low Power, SoC Encounter™ RTL-to-GDSII system, VoltageStorm® power and power rail verification