Altera and Cadence Joint Techtorial
This techtorial will show you how to integrate advanced, large-pin-count FPGAs on PCBs faster and how to cut your FPGA prototype bring up time. It will introduce Altera’s Stratix IV E FPGAs and the unique Cadence solution for FPGA/PCB Co-design. Also included is a hands-on workshop with the Cadence® Allegro® FPGA System Planner where you will learn how to:
- Shorten the time to perform correct-by-construction, route-aware pin assignment synthesis of one or more FPGAs on a PCB
- Achieve better FPGA performance through optimum utilization of FPGA resources
- Eliminate unnecessary iterations among FPGA designers, hardware designers, and PCB layout designers
Who should attend?
- FPGA designers
- ASIC/SoC designers
- PCB hardware designers
- Verification engineers
- Design group managers
- Engineering Managers
- Project managers
Agenda
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09:30 - 10:00 |
Registration |
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10:00 - 11:00 |
Altera Stratix IV E FPGAs |
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11:00 - 12:00 |
Cadence Allegro FPGA System Planner |
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12:00 - 1:00 |
Lunch/Demo Over Lunch |
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1:00 - 4:00 |
Allegro FPGA System Planner hands-on workshop using Altera Stratix IV E* |
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4:00 - 4:15 |
Wrap-up/Survey |
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Locations
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February 09, 2010 - Orlando, FL |
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February 10, 2010 - San Diego, CA |
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February 12, 2010 - Plano, TX |
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February 16, 2010 - Denver, CO |
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February 17, 2010 - Schaumburg, IL |
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February 19, 2010 - Chelmsford, MA |
Join us for this free techtorial and explore the latest technology and integrated design flows – new capabilities that will help you design higher-performance FPGAs on PCBs, increase productivity, and speed your time to market.
Questions about this event? Send email to events@cadence.com
Click here to register: http://www.secure-register.net/cadence/Altera-Cadence_FPGA_techtorials
*Seats for the hands-on workshop are limited and will be allocated on a first come first serve basis. Register soon to reserve your seat.
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