Coverage-Driven Verification

Using methodology and automation to solve your functional verification challenges

Overview

The functional verification challenge has never been so great.  With ASICs and even FPGAs now in the multi-million gate range, verification engineers need to generate and manage thousands of tests, deal with frequent spec changes, review project plans, and coordinate multiple teams/sites.  While EDA tools play an important role in addressing these issues, advanced methodologies are becoming critical. Teams must begin projects “with the end in mind”. For example they should setup verification metrics that are directly tied to the DUT’s specifications, and closley track changes throughout the project.  As metrics are captured in an easy to read, executable form, the verification process (along with all the supporting stimulus generation, simulation, and debug activities) becomes much more automated.  This will provide much higher levels productivity, predictability, and product quality and deliver on the promise of “coverage-driven verification”.

This techtorial will address the various productivity, predictability and quality risks that threaten all complex verification efforts. 

You will learn:

•  The principals of coverage-driven verification, independent of the underlying language used.
• How various forms of coverage including functional coverage, code coverage, formal and dynamic assertion coverage, and firmware code coverage are utilized to create a broader "metric driven" approach to verification.
• How to use the Open Verification Methodology (OVM) to rapidly create scalable, multi-language coverage-driven verification environments.
• How to create an executable verification plan to automate the recording and analysis of functional coverage & other metrics.
• How to automatically bind the verification plan to the MS Word or Framemaker device specification so any spec changes are automatically tracked, and the relevant metrics are easily recorded, analyzed, and reported to management.

Registration URL: http://www.secure-register.net/cadence/incisive_techtorials

Agenda

9:00am Registration/Breakfast

9:30am Introduction to Advanced Verification

9:45am Coverage Driven Verification

10:15am Metric Driven Verification: Incisive Plan to Closure Methodology          

10:45am Break

11:00am Open Verification Methodology (“OVM”)

11:30am  IEEE standard Hardware Verification Languages

12:00am Aspect Oriented vs. Object Oriented Programming

12:30pm Lunch (provided) and “E-Planner” Demo - automating the spec

1:00pm Workshop prep: Quick introduction to Incisive Enterprise Simulator

1:30pm – 4:30pm  Workshops/Tutorials

The afternoon session consists of several parallel workshops during which students will be able to apply many of the concepts detailed in the morning sessions in a “hands-on” format. Laptop computers loaded with the latest version of the Cadence technologies and flows will be used, allowing students to work through a tutorial-based manual with assistance from our Field Applications Engineering team. No prerequisite knowledge of the specific design solutions is required.

Afternoon Workshop & Tutorials

Attendees of this workshop will understand how a reusable component is structured, how to use an executable verification plan to analyze coverage results, run a simulation to understand how stimulus is generated, and create a bottom up verification plan.

Module 1
Review and understand the correct structure of a reusable component.

Module 2

§      Use an executable verification plan to analyze test runs.

§ Analyze the relative contribution of each run to the total coverage

Module 3

§  Launch a simulation and become familiar with the main GUI windows/panes

§  Look at some code to understand the intent of the test

Ø Stimulus data structure

Ø Activity to expect in the test

§ Run the simulation and understand how to view the main activity in the simulation, including traversing messages and waveforms

§ Review the Functional Coverage output

Module 4

Create a bottom-up verification plan using Enterprise Planner and utilizing several different sources, getting a head start from a Verification Plan that is provided with the UART UVC.  With this executable “vplan”, you will track the Coverage produced by the UART UVC and ICC coverage that is provided by the APB-UART Design itself

 Registration URL: http://www.secure-register.net/cadence/incisive_techtorials