Cadence Rapid System-Level Verification Techtorial

A Complete Holistic Verification Solution for System-on-Chip Designs

Overview

Achieving complete system verification and validation closure is among the most important challenges faced by designers and verification engineers. The ability to run multiple engines in multiple levels of abstraction and verify hardware and software in parallel increases system quality and helps teams meet schedules throughout the development process. The results include achieving first silicon working with first software.

This techtorial will cover the unique Cadence solution to this challenge through lectures, industry speakers, and case studies. It will also help you understand and leverage the latest products and flows that constitute the Cadence system-level verification methodology. This event is free and includes complimentary breakfast and lunch.

Register now at: http://www.secure-register.net/cadence/incisive_techtorials

Highlights include:

  • Transaction-level modeling
  • Transaction-based acceleration
  • SystemC simulation
  • In-circuit emulation
  • Acceleration of constrained-random coverage-driven verification
  • HW/SW co-verification

Agenda Overview:

  • Registration: 9:30a.m.  -  10:00am
  • Introduction: 10:00a.m.  -  10:15a.m.
  • High Performance System-Level Simulation: 10:15a.m.  - 11:00a.m.
  • Best Practices on How to Verify the Interaction of SoC Hardware and Software: 11:00a.m.  - 11:45a.m.
  • Application: Customer Case Study, QLogic: 11:45a.m. - 12:15p.m.
  • Lunch Break: 12:15a.m. - 12:45p.m.
  • Hands on ARM-Based Emulation demonstration: 12:45p.m. - 1:30p.m.
  • Wrap up and Raffle


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