Advanced Verification Techtorial

Give yourself the methodology & automation to solve your
functional verification challenges

OVERVIEW

Functional verification challenges have never been so great. With ASIC's and even FPGA's now in the multi-million gate range, Verification Engineers need to generate and manage thousands of tests, deal with frequent changes to the DUT spec and project plan, and coordinate multiple teams/sites. While EDA tools play an important role in addressing these issues, now more than ever advanced methodologies are critical to begin the project "with the end in mind" - to setup metrics for verification success that are directly tied to the DUT's specifications, and track any changes as closely as possible. When such metrics are captured in an easy to read, executable form, the verification process itself -- along with all the supporting formal analysis, stimulus generation, simulation, and debug activities -- can be automated to yield new gains in productivity, predictability, and quality. This is the process and promise of "metric driven verification".

By attending this techtorial, you will learn how to reduce the various productivity, predictability and quality risks that threaten all complex verification efforts. Specifically, you will learn:

• The principals of metric driven verification.
• How to create an executable verification, and bind this plan to the MS Word or Acrobat device specification so any spec changes are automatically tracked, and the relevant metrics are easily recorded, analyzed, and reported to management.
• How functional coverage can be combined with code coverage, formal and dynamic assertion coverage, and firmware code coverage to create a broader "metric driven" approach to verification.
• How to use the Open Verification Methodology (OVM) to rapidly create scalable, multi-language coverage driven verification environments.
• How to leverage formal analysis to find hard to reach bugs and decrease time to market.

All attendees will be entered into a drawing to win a grand prize. Drawing will be held at the end of the day and the winner must be present.

Space is limited. Sign up today at: http://www.secure-register.net/cadence/incisive_techtorials

Agenda

9:00am Registration / Breakfast
9:15am Components of Advanced Verification
10:00am Setting up for success: Verification Planning & Management
10:45am 15 minute Break
11:00am Getting a head start on verification with Formal Analysis Technology
11:40am Structured, Scalable Testbenches
12:20pm Summary
12:30pm Lunch (provided) & Workshop Registration
1:15pm Techtorial Introduction & Orientation
1:30pm - 4:00pm Workshops/Tutorials

The afternoon session consists of several workshops during which students will be able to apply many of the concepts detailed in the morning sessions in a "hands-on" format. Laptop computers loaded with the latest version of the Cadence technologies and flows will be used, allowing students to work through a tutorial-based manual with assistance from our Field Applications Engineering team. No prerequisite knowledge of the specific design solutions is required.

Module 1
How to get a head start on verification without a testbench, using assertions to get the most out of formal verification technology.

 
Module 2 How verification planning and project management goals can be synthesized from the DUT and test specification into an executable verification plan using "Enterprise Planner".

Module 3
How to leverage OVM-compliant verification components to rapidly create reusable, constrained-random scenarios that stimulate activity in multiple elements of a testbench; and then record important coverage metrics as the scenarios play out.

Module 4
Using the executable "vPlan" and verification environment created in the previous modules, you will track the Coverage and analyze simulation failures in the DUT with the "Enterprise Manager".