Cadence Transaction Level Design and Verification
Transaction level modeling (TLM) is a new approach to creating designs and performing functional verification. Beginning your project with TLM provides productivity, quality and IP reuse benefits that cannot be achieved using RTL. Technologies for performing TLM design synthesis and functional verification have been emerging for several years. Only recently has a comprehensive solution been developed for TLM-driven design, verification, and reuse.
This techtorial is designed for systems engineers, hardware designers, verification engineers, and managers who want to increase the productivity of their team, and the quality of their systems designs. Attendees will be given a full day workshop with hands-on labs, providing instruction on TLM -driven design and verification methodology, with separate but similar lab tracks for participants focused on design and those focused on verification. This dual-lab approach gives each participant a full experience while focusing on their responsibility.
The solution includes Cadence® Incisive® and C-to-Silicon Compiler®, TLM design synthesis subset, and TLM verification using the Open Verification Methodology (OVM).
You will learn
- How to design transaction level models (TLM)
- How to perform TLM and RTL functional verification
- How to perform TLM synthesis to RTL and to the gate level
- How design and verification IP reuse is enabled
Who Should Attend
- Verification or Design Engineers
- Architects and Project Managers
Space is limited. Sign up today at http://www.secure-register.net/cadence/incisive_techtorials
Agenda
8::30am - Registration / Breakfast
9:00am - TLM-driven Design and Verification Introduction
- Introduction to transaction level design and verification
- Benefits of productivity, quality, and IP reuse
9:30am - Creating a TLM Design
- Introduction to SystemC transaction level modeling (TLM)
- Basic TLM Design Topics (+ lab)
11:00am - Verifying a TLM Design
- TLM functional verification concepts
- Applying Metric Driven Verification to TLM (+ lab)
12:30 - LUNCH (Provided)
1:30pm - Synthesizing a TLM Design
- TLM Synthesis and QoR (+ lab)
3:00pm - Verifying the resulting RTL
- Reuse of Verification from TLM
3:30pm - TLM Design and Verification Reuse
- How reuse of IP is enabled
- Multiple reuse opportunities for TLM design and verification IP
4:00pm - Program end
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