SoC I/O Padring Optimization using Cadence SiP Co-Design Technology
Do you struggle to integrate your SoC or large ASIC into the IC package? Do you use spreadsheets to manage the I/O padring interface between the chip and package? Is your current process time consuming, not achieving your desired results for managing package costs/complexity, nor achieving target die size? This webinar targets IC designers who are interested in optimizing the I/O padring. IC designers will be able to look at the padring in the context of the package and PCB, and use automated technology to minimize crossovers so that package and board interconnect can be simplified and overall system cost will be reduced. This webinar will feature the Cadence® SiP solution and its ability to help IC designers optimize the I/O padring. Attendees will be shown how to use components on the PCB to determine optimal placement of I/Os on the chip as well as the optimal locations for balls of the BGA. The end result is fewer layers on the package as well as PCBs that are easier to route. Attendees will receive an overview and demonstration of the capabilities, advantages, and benefits of the Cadence SiP co-design technology for I/O padring optimization. Who Should Attend
Date/TimeAugust 26, 2009 - Webinar, at your desktop : 7:00 AM - 8:00 AM PST August 26, 2009 - Webinar, at your desktop : 11:00 AM - 12:00 PM PST (http://timeanddate.com/worldclock/)
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