Best Practices and Methods for Mixed-Signal Verification Webinar
Date: November 18, 2009
Time: 8:00am PST / 11:00 am EST / 5:00pm CET
Duration: 60 minutes
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- Is mixed-signal verification a major bottleneck within your IC design and verification flow?
- Are you part of an analog/mixed-signal design team that is required to deliver a high-quality functional “digital-ONLY” simulation net list to a digital verification organization as part of SoC verification?
If you answered yes to the above questions, attend this webinar and learn how Cadence® Services can help you:
- Reduce risk and boost verification productivity to obtain first-pass functional silicon
- Establish a scalable mixed-signal functional verification methodology
- Improve the quality of block signoff (compliance) and signal-path verification, thereby increasing the chance of first-pass spec-compliant silicon
Part of the Cadence Services Webinar Series, this webinar will introduce you to the following packaged services offerings:
- Mixed-signal functional verification – Behavioral modeling is the key technology to enable comprehensive mixed-signal functional verification. Cadence Services has been on the leading edge of behavioral modeling development as applied to mixed-signal functional verification for several years. This service will enable any IC mixed-signal design and verification organization to establish verification capability for:
- AMS flow (uses analog/mixed-signal simulation)
- DMS flow (uses digital-ONLY simulation)
- Mixed-signal signal-path (spec) verification – Cadence Services will work with you to evaluate your current signal-path verification methods for the purpose of improving your signal-path verification process. This service focuses on block-level specifications and how to model this behavior to increase simulation throughput.
Cadence Services can also provide:
- Mixed-signal verification assessment of your current methodology related to these two different verification processes (AMS/DMS and signal-path). We offer expert recommendations, deliver metrics of your verification process and environment, and compare the results to industry best practices.
Who should attend?
- RF and AMS IC design engineers
- Verification engineers and managers
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